Operator Library: Hardware Platform
The DFTxMeta operator represents a logical metadata transmission link over QSFP28 fiber port on the specified fiber lane within the chosen port on the input I to another frame grabber. Additionally, the status of the TX PHY is provided on the output LinkUp.
The DFTxMeta operator can be used only if the FiberProtocol0 and FiberProtocol1 parameters in the AppletProperties operator are set to DataForwarding. If the FiberProtocol0 and FiberProtocol1 parameters in the AppletProperties operator are set to CoF, the Design Rules Check (DRC) provides an error message and the DFTxMeta operator usage is blocked.
The operator can span only 1 lane within a QSFP28 port for the metadata transmission. This means that a single QSFP28 port can be used by maximum 4 DFTxMeta operators. The operator is meant to transport high priority meta information, which is usually very small.
A QSFP28 fiber port provides a total bandwidth of 100 Gbit/s, divided across four lanes. Each lane operates at 25 Gbit/s. Thus, the operator is running at 25 Gbit/s.
The operator can share its allocated lane with the DFTxData operator without conflict. But lane sharing between DFTxMeta operators is prohibited.
The DFTxMeta operator does not expect any special protocol. It represents the start point of a logic high priority link between 2 frame grabbers from DFTxMeta (frame grabber 1) to DFRxMeta (frame grabber 2). The settings of the link must be identical for the source and sink operators, i.e., exactly the same QSFP28 port and lane configuration. Since the operator is meant for transporting small chunks of metadata, the link protocol is VALT_PIXEL0D and metadata has no image structure.
![[Note]](../common/images/admon/note.png) |
Meta Data Has Higher Priority |
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The metadata channel has higher priority than the data channel from the DFTxData operator. If both channels are waiting to transmit data, the metadata will be transmitted first. |
The meta channel can be paused or stopped, but only for very short time. Meta data channel has a very low latency and almost no jitter (< 10 ns due to clock domain crossings). The meta channel is suitable not only for metadata transport, but it can be used also for transmitting user-precise time stamps or to implement a system-wide synchronization.
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Internal Clock Frequency |
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The transmission is running internally at 390.625 MHz. When the FPGA Clock is set higher, the internal clock domain crossing buffer in the DFTxMeta operator will automatically run full and stop the operator input I to accept new data. This must be considered when sending time stamps or doing board-to-board synchronization. |
For more details about data forwarding, see 'Data Forwarding with imaFlex 2 Dual 100 Frame Grabbers'.
| Available for Hardware Platform |
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| imaFlex 2 Dual 100 |
Resources
The operator mirrors the FiberConnection parameter setting into the dialog as read-only parameters. You can see the FPGA device resources, if you open the dialog from the menu. The device resources are read-only:
Depending on the allocated port, the resource is of the type Port[0] DF TX Meta Lane or of the type Port[1] DF TX Meta Lane with the index range from 0 to 3.
| Property | Value |
|---|---|
| Operator Type | M |
| Input Link | I, metadata input, stoppable |
| Output Link | LinkUp, indicates link status |
| Link Parameter | Input Link I | Output Link LinkUp |
|---|---|---|
| Bit Width | 56 | 1 |
| Arithmetic | unsigned | unsigned |
| Parallelism | 1 | 1 |
| Kernel Columns | 1 | 1 |
| Kernel Rows | 1 | 1 |
| Img Protocol | {VALT_PIXEL0D} | {VALT_SIGNAL} |
| Color Format | VAF_GRAY | VAF_GRAY |
| Color Flavor | FL_NONE | FL_NONE |
| Max. Img Width | any (default: 16777216) | don't care |
| Max. Img Height | any (default: 16777216) | don't care |
The link I accepts transmission metadata from VisualApplets. The link LinkUp indicates the status of the link. When it is set, the paired TX side and the RX side are both ready to transmit and receive data, meaning the link is trained and operational.
| FiberConnection | |
|---|---|
| Type | Static Write parameter |
| Default | port_0_lane_0 |
| Range | {port_0_lane_0, port_0_lane_1, port_0_lane_2, port_0_lane_3, port_1_lane_0, port_1_lane_1, port_1_lane_2, port_1_lane_3} |
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This parameter specifies the QSFP28 fiber port and lanes used by the DFTxMeta operator to transmit data. The selected QSFP28 port can be used only if the FiberProtocol parameter in the AppletProperties operator for that port is set to DataForwarding and not to CoF. If FiberProtocol is set to CoF and the DFTxMeta operator attempts to map to that fiber port, the Design Rule Check (DRC) will generate an error message. In this case, the FiberConnection parameter will be marked as conflicted (red), and hovering over it will display a quick-tip help message explaining the conflict. Only one DFTxMeta operator can use the same hardware QSFP28 port on the same lane. Mappings between multiple operators must be unique across the entire design. |
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The use of operator DFTxMeta is shown in the following examples:
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'Data Forwarding on imaFlex2 Dual 100 Platform'
The examples show how data forwarding can be implemented on imaFlex 2 Dual 100 platforms.
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